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single-channel, 1024-position, 1% r-tolerance digital potentiometer ad5293 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2011 analog devices, inc. all rights reserved. features single-channel, 1024-position resolution 20 k, 50 k, and 100 k nominal resistance calibrated 1% nominal resistor tolerance (resistor performance mode) rheostat mode temperature coefficient: 35 ppm/c voltage divider temperature coefficient: 5 ppm/c single-supply operation: 9 v to 33 v dual-supply operation: 9 v to 16.5 v spi-compatible serial interface wiper setting readback applications mechanical potentiometer replacement instrumentation: gain and offset adjustment programmable voltage-to-current conversion programmable filters, delays, and time constants programmable power supply low resolution dac replacements sensor calibration functional block diagram a w b rdac register 10 serial interface sync sclk din power-on reset v logic sdo ext_cap v dd v ss gnd ad5293 reset rdy 07675-001 figure 1. general description the ad5293 is a single-channel, 1024-position digital potentiometer 1 with a <1% end-to-end resistor tolerance error. the ad5293 performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. this device is capable of operating at high voltages and supporting both dual-supply operation at 10.5 v to 15 v and single-supply operation at 21 v to 30 v. the ad5293 offers guaranteed industry-leading low resistor tolerance errors of 1% with a nominal temperature coefficient of 35 ppm/c. the low resistor tolerance feature simplifies open- loop applications as well as precision calibration and tolerance matching applications. the ad5293 is available in a compact 14-lead tssop package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +105c. 1 in this data sheet, the terms digital potentiometer and rdac are used interchangeably.
ad5293 rev. d | page 2 of 24 table of contents features ...............................................................................................1 ? applications........................................................................................1 ? functional block diagram ...............................................................1 ? general description ..........................................................................1 ? revision history ................................................................................2 ? specifications......................................................................................3 ? electrical characteristics20 k versions ...............................3 ? resistor performance mode code range20 k versions ...4 ? electrical characteristics50 k and 100 k versions..........5 ? resistor performance mode code range50 k and 100 k versions...........................................................................................6 ? interface timing specifications...................................................7 ? timing diagrams...........................................................................8 ? absolute maximum ratings.............................................................9 ? thermal resistance .......................................................................9 ? esd caution...................................................................................9 ? pin configuration and function descriptions........................... 10 ? typical performance characteristics ........................................... 11 ? test circuits..................................................................................... 17 ? theory of operation ...................................................................... 18 ? serial data interface................................................................... 18 ? shift register ............................................................................... 18 ? rdac register............................................................................ 18 ? write protection ......................................................................... 18 ? basic operation .......................................................................... 18 ? shutdown mode.......................................................................... 18 ? reset ............................................................................................. 19 ? resistor performance mode...................................................... 19 ? sdo pin and daisy-chain operation ..................................... 19 ? rdac architecture .................................................................... 20 ? programming the variable resistor......................................... 20 ? programming the potentiometer divider ............................... 21 ? ext_cap capacitor.................................................................. 21 ? terminal voltage operating range.......................................... 21 ? applications information .............................................................. 22 ? high voltage dac...................................................................... 22 ? programmable voltage source with boosted output............ 22 ? high accuracy dac .................................................................. 22 ? variable gain instrumentation amplifier............................... 22 ? audio volume control .............................................................. 23 ? outline dimensions ....................................................................... 24 ? ordering guide........................................................................... 24 ? revision history 3/11rev. c to rev. d changes to table 1, endnote 2 ................................................................ 4 changes to table 3, endnote 2........................................................ 6 9/10rev. b to rev. c added cpol = 0, cpha = 1 to figure 3 and figure 4 captions..... 8 changes to sdo pin and daisy-chain operation section....... 19 3/10rev. a to rev. b changes to resistor noise density conditions (table 3) ........... 6 12/09rev. 0 to rev. a added 50 k and 100 k specifications.........................universal changes to features section............................................................ 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 added table 3; renumbered sequentially .................................... 5 added table 4.................................................................................... 6 changes to table 5............................................................................ 7 changes to table 6 and note 1, table 7 ......................................... 9 changes to typical performance characteristics section......... 11 changes to programming the variable resistor section .......... 20 changes to programming the potentiometer divider section ............................................................................... 21 changes to ordering guide section ............................................ 24 4/09revision 0: initial version
ad5293 rev. d | page 3 of 24 specifications electrical characteristics20 k versions v dd = 21 v to 33 v, v ss = 0 v; v dd = 10.5 v to 16.5 v, v ss = ?10.5 v to ?16.5 v; v logic = 2.7 v to 5.5 v, v a = v dd , v b = v ss , ?40c < t a < +105c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resolution n 10 bits resistor differential nonlinearity 2 r-dnl r wb ?1 +1 lsb resistor integral nonlinearity 2 r-inl |v dd ? v ss | = 26 v to 33 v ?2 +2 lsb r-inl |v dd ? v ss | = 21 v to 26 v ?3 +3 lsb nominal resistor tolerance (r-perf mode) 3 ?r ab /r ab see table 2 ?1 0.5 +1 % nominal resistor tolerance (normal mode) ?r ab /r ab 7 % resistance temperature coefficient 4 (?r ab /r ab )/?t 10 6 35 ppm/c wiper resistance r w 60 100 dc characteristics, potentiometer divider mode resolution n 10 bits differential nonlinearity 5 dnl ?1 +1 lsb integral nonlinearity 5 inl ?1.5 +1.5 lsb voltage divider temperature coefficient 4 (?v w /v w )/?t 10 6 code = half scale 5 ppm/c full-scale error v wfse code = full scale ?8 0 lsb zero-scale error v wzse code = zero scale 0 8 lsb resistor terminals terminal voltage range 6 v a , v b , v w v ss v dd v capacitance a, capacitance b 4 c a , c b f = 1 mhz, measured to gnd, code = half-scale 85 pf capacitance w 4 c w f = 1 mhz, measured to gnd, code = half-scale 65 pf common-mode leakage current i cm v a = v b = v w 1 na digital inputs jedec compliant input logic high v ih v logic = 2.7 v to 5.5 v 2.0 v input logic low v il v logic = 2.7 v to 5.5 v 0.8 v input current i il v in = 0 v or v logic 1 a input capacitance 4 c il 5 pf digital outputs (sdo and rdy) output high voltage v oh r pull_up = 2.2 k to v logic v logic ? 0.4 v output low voltage v ol r pull_up = 2.2 k to v logic gnd + 0.4 v tristate leakage current ?1 +1 a output capacitance 4 c ol 5 pf power supplies single-supply power range v dd v ss = 0 v 9 33 v dual-supply power range v dd /v ss 9 16.5 v positive supply current i dd v dd /v ss = 16.5 v 0.1 2 a negative supply current i ss v dd /v ss = 16.5 v ?2 ?0.1 a logic supply range v logic 2.7 5.5 v logic supply current i logic v logic = 5 v; v ih = 5 v or v il = gnd 1 10 a power dissipation 7 p diss v ih = 5 v or v il = gnd 8 110 w power supply rejection ratio 4 pssr ?v dd /?v ss = 15 v 10% 0.103 %/%
ad5293 rev. d | page 4 of 24 parameter symbol conditions min typ 1 max unit dynamic characteristics 4 , 8 bandwidth bw ?3 db 520 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, ?93 db v w settling time t s v a = 30 v, v b = 0 v, 0.5 lsb error band, initial code = zero scale code = full scale, r-normal mode 750 ns code = full scale, r-perf mode 2.5 s code = half scale, r-normal mode 2.5 s code = half scale, r-perf mode 5 s resistor noise density e n_wb r wb = 10 k, t a = 25c, 0 khz to 200 khz 10 nv/hz 1 typicals represent average readings at 25c; v dd = +15 v, v ss = ?15 v, and v logic = 5 v. 2 resistor position nonlinearity error. r-inl is the deviation from an ideal value measured between r wb at code 0x00b to code 0x3ff or between r wa at code 0x3f3 to code 0x000. r-dnl measures the relative st ep change from ideal between successive tap positions. the specification is guarantee d in resistor performance mode with a wiper current of 1 ma for v a < 12 v and 1.2 ma for v a 12 v. 3 the terms resistor performance mode and r-perf mode are used interchangeably. 4 guaranteed by design; not subject to production test. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. du al-supply operation enables g round-referenced bipolar signal adjustment. 7 p diss is calculated from (i dd v dd ) + (i ss v ss ) + (i logic v logic ). 8 all dynamic characteristics use v dd = +15 v, v ss = ?15 v, and v logic = 5 v. resistor performance mode code range20 k versions table 2. r ab = 20 k |v dd ? v ss | = 30 v to 33 v |v dd ? v ss | = 26 v to 30 v |v dd ? v ss | = 22 v to 26 v |v dd ? v ss | = 21 v to 22 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x15e to 0x3ff from 0x000 to 0x2a1 from 0x1f4 to 0x3ff from 0x000 to 0x20b from 0x1f4 to 0x3ff from 0x000 to 0x20b n/a n/a 2% r-tolerance from 0x8c to 0x3ff from 0x000 to 0x373 from 0xb4 to 0x3ff from 0x000 to 0x34b from 0xfa to 0x3ff from 0x000 to 0x305 from 0xfa to 0x3ff from 0x000 to 0x305 3% r-tolerance from 0x5a to 0x3ff from 0x000 to 0x3a5 from 0x64 to 0x3ff from 0x000 to 0x39b from 0x78 to 0x3ff from 0x000 to 0x387 from 0x78 to 0x3ff from 0x000 to 0x387
ad5293 rev. d | page 5 of 24 electrical characteristics50 k and 100 k versions v dd = 21 v to 33 v, v ss = 0 v; v dd = 10.5 v to 16.5 v, v ss = ?10.5 v to ?16.5 v; v logic = 2.7 v to 5.5 v, v a = v dd , v b = v ss , ?40c < t a < +105c, unless otherwise noted. table 3. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resolution n 10 bits resistor differential nonlinearity 2 r-dnl r wb ?1 +1 lsb resistor integral nonlinearity 2 r-inl ?2 +2 lsb nominal resistor tolerance (r-perf mode) 3 ?r ab /r ab see table 4 ?1 0.5 +1 % nominal resistor tolerance (normal mode) ?r ab /r ab 20 % resistance temperature coefficient 4 (?r ab /r ab )/?t 10 6 35 ppm/c wiper resistance r w 60 100 dc characteristics, potentiometer divider mode resolution n 10 bits differential nonlinearity 5 dnl ?1 +1 lsb integral nonlinearity 5 inl ?1.5 +1.5 lsb voltage divider temperature coefficient 4 (?v w /v w )/?t 10 6 code = half scale 5 ppm/c full-scale error v wfse code = full scale ?8 +1 lsb zero-scale error v wzse code = zero scale 0 8 lsb resistor terminals terminal voltage range 6 v a , v b , v w v ss v dd v capacitance a, capacitance b 4 c a , c b f = 1 mhz, measured to gnd, code = half-scale 85 pf capacitance w 4 c w f = 1 mhz, measured to gnd, code = half-scale 65 pf common-mode leakage current i cm v a = v b = v w 1 na digital inputs jedec compliant input logic high v ih v logic = 2.7 v to 5.5 v 2.0 v input logic low v il v logic = 2.7 v to 5.5 v 0.8 v input current i il v in = 0 v or v logic 1 a input capacitance 4 c il 5 pf digital outputs (sdo and rdy) output high voltage v oh r pull_up = 2.2 k to v logic v logic ? 0.4 v output low voltage v ol r pull_up = 2.2 k to v logic gnd + 0.4 v tristate leakage current ?1 +1 a output capacitance 4 c ol 5 pf power supplies single-supply power range v dd v ss = 0 v 9 33 v dual-supply power range v dd /v ss 9 16.5 v positive supply current i dd v dd /v ss = 16.5 v 0.1 2 a negative supply current i ss v dd /v ss = 16.5 v ?2 ?0.1 a logic supply range v logic 2.7 5.5 v logic supply current i logic v logic = 5 v; v ih = 5 v or v il = gnd 1 10 a power dissipation 7 p diss v ih = 5 v or v il = gnd 8 110 w power supply rejection ratio 4 pssr ?v dd /?v ss = 15 v 10% r ab = 50 k 0.039 %/% r ab = 100 k 0. 021 %/%
ad5293 rev. d | page 6 of 24 parameter symbol conditions min typ 1 max unit dynamic characteristics 4 , 8 bandwidth bw ?3 db khz r ab = 50 k 210 r ab = 100 k 105 total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 50 k ?101 db r ab = 100 k ?106 db v w settling time t s v a = 30 v, v b = 0 v, 0.5 lsb error band, initial code = zero scale code = full scale, r-normal mode 750 ns code = full scale, r-perf mode 2.5 s code = half scale, r-normal mode, r ab = 50 k 7 s code = half scale, r-normal mode, r ab = 100 k 14 s code = half scale, r-perf mode, r ab = 50 k 9 s code = half scale, r-perf mode, r ab = 100 k 16 s resistor noise density e n_wb code = half scale, t a = 25c, 0 khz to 200 khz, r ab = 50 k 18 nv/hz r ab = 100 k 27 nv/hz 1 typicals represent average readings at 25c; v dd = +15 v, v ss = ?15 v, and v logic = 5 v. 2 resistor position nonlinearity error. r-inl is the deviation from an ideal value measured between r wb at code 0x00b to code 0x3ff or between r wa at code 0x3f3 to code 0x000. r-dnl measures the relative st ep change from ideal between successive tap positions. the specification is guarantee d in resistor performance mode with a wiper current of 1 ma for v a < 12 v and 1.2 ma for v a 12 v. 3 the terms resistor performance mode and r-perf mode are used interchangeably. 4 guaranteed by design; not subject to production test. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. du al-supply operation enables g round-referenced bipolar signal adjustment. 7 p diss is calculated from (i dd v dd ) + (i ss v ss ) + (i logic v logic ). 8 all dynamic characteristics use v dd = +15 v, v ss = ?15 v, and v logic = 5 v. resistor performance mode code range50 k and 100 k versions table 4. r ab = 50 k r ab = 100 k |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x08c to 0x3ff from 0x000 to 0x35f from 0x0b4 to 0x3ff from 0x000 to 0x31e from 0x04b to 0x3ff from 0x000 to 0x3b4 from 0x064 to 0x3ff from 0x000 to 0x39b 2% r-tolerance from 0x03c to 0x3ff from 0x000 to 0x3c3 from 0x050 to 0x3ff from 0x000 to 0x3af from 0x028 to 0x3ff from 0x000 to 0x3d7 from 0x028 to 0x3ff from 0x000 to 0x3d7 3% r-tolerance from 0x028 to 0x3ff from 0x000 to 0x3d7 from 0x032 to 0x3ff from 0x000 to 0x3cd from 0x019 to 0x3ff from 0x000 to 0x3e6 from 0x019 to 0x3ff from 0x000 to 0x3e6
ad5293 rev. d | page 7 of 24 interface timing specifications v dd = v ss = 15 v, v logic = 2.7 v to 5.5 v, and ?40c < t a < +105c. all specifications t min to t max , unless otherwise noted. table 5. parameter limit 1 unit test conditions/comments t 1 2 20 ns min sclk cycle time t 2 10 ns min sclk high time t 3 10 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 1 ns min sclk falling edge to sync rising edge t 8 400 3 ns min minimum sync high time t 9 14 ns min sync rising edge to next sclk fall ignored t 10 4 1 ns min rdy rise to sync falling edge t 11 4 40 ns max sync rise to rdy fall time t 12 4 2.4 s max rdy low time, rdac register write command execute time (resistor performance mode) t 12 4 410 ns max rdy low time, rdac register write command execute time (normal mode) t 12 4 1.5 ms max software\hardware reset t 13 4 450 ns max rdy low time, rdac register read command execute time t 14 4 450 ns max sclk rising edge to sdo valid t reset 20 ns min minimum reset pulse width (asynchronous) t power-up 5 2 ms max power-on time to half scale 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency = 50 mhz. 3 refer to t 12 and t 13 for rdac register commands operations. 4 r pull_up = 2.2 k to v logic with a capacitance load of 168 pf. 5 typical power supply voltage slew-rate of 2 v/ms. data bits db9 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 control bits c0c1 c2 d9 d8 c3 00 07675-002 figure 2. shift register contents
ad5293 rev. d | page 8 of 24 timing diagrams t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 x sync sclk t 9 t 1 t 8 din sdo d6 d7 d2 xc3 c2 rdy t 12 t 10 t 11 07675-003 reset t reset figure 3. write timing diagram, cpol = 0, cpha =1 d0 d1 x sync sclk t 9 t 14 t 13 t 11 din sdo x d0 x xc3 rdy d0 x x c3 d0 d1 c3 0 7675-004 figure 4. read timing diagram, cpol = 0, cpha =1
ad5293 rev. d | page 9 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to +35 v v ss to gnd +0.3 v to ?25 v v logic to gnd ?0.3 v to +7 v v dd to v ss 35 v v a , v b , v w to gnd v ss ? 0.3 v, v dd + 0.3 v digital input and output voltage to gnd ?0.3 v to v logic +0.3 v ext_cap voltage to gnd ?0.3 v to +7 v i a , i b , i w continuous r ab = 20 k 3 ma r ab = 50 k, 100 k 2 ma pulsed 1 frequency > 10 khz mcc 2 /d 3 frequency 10 khz mcc 2 /d 3 operating temperature range ?40c to +105c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja jc unit 14-lead tssop 93 1 20 c/w 1 jedec 2s2p test board, still air (from 0 m/sec to 1 m/sec of air flow). esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 maximum continuous current. 3 pulse duty factor.
ad5293 rev. d | page 10 of 24 pin configuration and fu nction descriptions reset v ss a w rdy sync v logic sclk b v dd ext_cap 1 2 3 4 5 6 7 din gnd 14 13 12 11 10 9 8 ad5293 top view not to scale sdo 07675-005 figure 5. pin configuration table 8. pin function descriptions pin o. mnemonic description 1 reset hardware reset pin. sets the rdac register to midscale. reset is activated at the logic high transition. tie reset to v logic if not used. 2 v ss negative supply. connect to 0 v for single-supply applications. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 3 a terminal a of rdac. v ss v a v dd . 4 w wiper terminal w of rdac. v ss v w v dd . 5 b terminal b of rdac. v ss v b v dd . 6 v dd positive power supply. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 7 ext_cap connect a 1 f capacitor to ext_cap. this capacitor must have a voltage rating of 7 v. 8 v logic logic power supply, 2.7 v to 5.5 v. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 9 gnd ground pin, logic ground reference. 10 din serial data input. this part has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 11 sclk serial clock input. data is clocked into the shift register on the falling edge of the serial clock input. data can be transferred at rates up to 50 mhz. 12 sync falling edge synchronization signal. this is the frame synchronization signal for the input data. when sync goes low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. the selected register is updated on the rising edge of sync , following the 16 th clock cycle. if sync is taken high before the 16 th clock cycle, the rising edge of sync acts as an interrupt, and the write sequence is ignored by the dac. 13 sdo serial data output. this open-drain o utput requires an external pull-up resi stor. sdo can be used to clock data from the serial register in daisy-chain mode or in readback mode. 14 rdy ready pin. this active-high, open-drain output identifies th e completion of a write or read operation to or from the rdac register.
ad5293 rev. d | page 11 of 24 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07675-106 r ab = 20k ? figure 6. r-inl in r-perf mode vs. code vs. temperature 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) 0 128 256 384 512 640 768 896 1023 code (decimal) +25c ?40c +105c 7 07675-00 r ab = 20k ? figure 7. r-dnl in r-perf mode vs. code vs. temperature 1.0 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) ?0.6 ?0.4 0 128 256 384 512 640 768 896 1023 code (decimal) +25c ?40c +105c 07675-010 r ab = 20k ? figure 8. r-inl in normal mode vs. code vs. temperature 07675-215 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 25c figure 9. r-inl in r-perf mode vs. code vs. nominal resistance 07675-211 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 10. r-dnl in r-perf mode vs. code vs. nominal resistance 07675-216 1.0 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 25c figure 11. r-inl in normal mode vs. code vs. nominal resistance
ad5293 rev. d | page 12 of 24 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07675-011 r ab = 20k ? figure 12. r-dnl in normal mo de vs. code vs. temperature 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07675-014 r ab = 20k ? figure 13. inl in r-perf mode vs. code vs. temperature 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.2 ?0.1 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07675-015 r ab = 20k ? figure 14. dnl in r-perf mode vs. code vs. temperature 07675-213 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 25c figure 15. r-dnl in normal mode vs. code vs. nominal resistance 07675-207 0.8 ?0.8 ?0.6 ?0.2 0 0.2 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 25c figure 16. inl in r-perf mode vs. code vs. nominal resistance 07675-203 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 17. dnl in r-perf mode vs. code vs. nominal resistance
ad5293 rev. d | page 13 of 24 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07675-018 r ab = 20k ? figure 18. inl in normal mode vs. code vs. temperature 0.10 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07675-019 r ab = 20k ? figure 19. dnl in normal mode vs. code vs. temperature 07675-022 450 400 350 300 250 200 150 100 50 0 ?50 supply current (na) temperature (c) ?40?30?20?100 102030405060708090100 i logic v dd /v ss = 15v v logic = +5v i dd i ss figure 20. supply current vs. temperature 07675-209 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k? 50k? 100k? temperature = 25c figure 21. dnl in normal mode vs. code vs. temperature 07675-205 0.08 ?0.16 ?0.12 ?0.08 ?0.04 0 0.04 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 25c figure 22. dnl in normal mode vs. code vs. temperature 07675-057 0.20 0.18 0.16 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply current i logic (ma) digital input voltage (v) v dd = 15v figure 23. supply current, i logic , vs. digital input voltage.
ad5293 rev. d | page 14 of 24 700 600 500 400 300 200 100 0 rheostat mode tempco (ppm/c) 07675-023 0 256 512 768 1023 code (decimal) 50k ? 20k? 100k? v dd = 30v, v ss = 0v figure 24. rheostat mode tempco r wb /t vs. code 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 1m 100k 10k 1k 100 10 07675-025 gain (db) frequency (hz) 0x200 0x100 0x080 0x040 0x020 0x010 0x008 0x004 0x002 0x001 figure 25. 20 k gain vs. frequency vs. code ?50 ?40 ?30 ?10 0 10 1m 100k 10k 1k 100 gain (db) frequency (hz) 0x200 0x080 0x020 0x010 0x004 0x002 0x001 ?20 ?60 07674-200 0x040 0x008 0x100 figure 26. 50 k gain vs. frequency vs. code 700 600 500 400 300 200 100 0 potentiometer mode tempco (ppm/c) 0 7675-024 0 256 512 768 1023 code (decimal) v dd = 30v v ss = 0v 50k ? 20k? 100k ? figure 27. potentiometer mode tempco r wb /t vs. code ?60 ?50 ?40 ?30 ?10 0 10 1m 100k 10k 1k 100 gain (db) frequency (hz) 0x200 0x100 0x080 0x040 0x020 0x010 0x008 0x004 0x002 0x001 ?20 ?70 07675-201 figure 28. 100 k gain vs. frequency vs. code ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k frequency (hz) 100k 1m 100k ? 20k ? 50k ? 07675-026 psrr (db) figure 29. power supply rejectio n ratio (psrr) vs. frequency
ad5293 rev. d | page 15 of 24 07675-027 0 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 thd + n (db) frequency (hz) 100 1k 10k 100k v dd /v ss = 15v code = half scale v in = 1v rms noise bw = 22khz 50k ? 20k ? 100k ? figure 30. total harmonic distortion + noise (thd + n) vs. frequency 0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 bandwidth (hz) 800,000 900,000 1,000,000 code (decimal) 512 0 128 256 64 32 16 8 07675-222 20k ? 0pf 20k ? 75pf 20k ? 150pf 20k ? 250pf 50k ? 0pf 50k ? 75pf 50k ? 150pf 50k ? 250pf 100k ? 0pf 100k ? 75pf 100k ? 150pf 100k ? 250pf figure 31. maximum bandwidth vs. code vs. net capacitance 07675-058 35 ?5 0 5 10 15 20 25 30 voltage (v) time (s) v wb , code: full scale, normal mode sync ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd /v ss = 30v/0v v logic = 5v v a = v dd v b = v ss v wb , code: half-scale, normal mode v wb , code: half-scale, r-perf mode 20k ? 50k ? 100k ? 20k ? 50k ? 100k ? v wb , code: full scale, r-perf mode figure 32. large signal settling time, code from zero scale to full scale ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0.001 0.01 0.1 1 10 thd + n (db) amplitude (v rms) 07675-220 v dd /v ss = 15v, code = half scale f in = 1khz noise bw = 22khz 50k ? 20k ? 100k ? figure 33. total harmonic distortion + noise (thd + n) vs. amplitud 8 0 1 2 3 4 5 6 7 0 256 512 768 1023 theoretical i wb_max (ma) code (decimal) 07675-029 v dd /v ss = 30v/0v v a = v dd v b = v ss 50k? 20k? 100k ? figure 34. theoretical maximum current vs. code 40 32 24 ? 40 ?32 ?24 ?16 ?8 0 8 16 ?0.5 0 5 10 15 20 25 30 35 40 45 voltage ( v) time (s) v dd /v ss = 15v v a =v dd v b =v ss code = half code 07675-221 figure 35. digital feedthrough
ad5293 rev. d | page 16 of 24 21 26 30 33 voltage v dd /v ss number of codes (ad5293) 80 0 10 20 30 40 50 60 70 07675-219 v a = v dd v b = v ss temperature = 25c 50k ? 20k ? 100k ? 07675-035 1.2 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 voltage (v) time (s) ?202 46 810121416 v dd /v ss = 15v v logic = +5v v a = v dd v b = v ss 50k ? 20k ? 100k ? figure 38. code range > 1% r-tolerance error vs. voltage figure 36. maximum transition glitch 07675-056 300 250 200 150 100 50 0 number of codes (ad5293) temperature (c) ?40?30?20?100 102030405060708090100 v dd /v ss = 15v 50k ? 20k ? 100k ? figure 37. code range > 1% r-tolerance error vs. temperature
ad5293 rev. d | page 17 of 24 test circuits figure 39 to figure 44 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 07675-030 figure 39. resistor position nonlinearity error (rheostat operation: r-inl, r-dnl) a w b dut v ms v+ v + = v dd 1lsb = v+/2 n 07675-031 figure 40. potentiometer divider nonlinearity error (inl, dnl) + ? dut code = 0x00 0.1v v ss to v dd r wb = 0.1 v i wb r w = r wb 2 i wb w b a = nc 0 76 75-032 figure 41. wiper resistance a w b v ms ~ v a v dd v+ v+ = v dd 10% ? v ms % ? v dd % pss (%/%) = psrr (db) = 20 log ? v ms ? v dd 07675-033 figure 42. power supply sensitivity (pss, psrr) 07675-036 offset gnd a b dut w +15 v v in v out op42 ?15v 2.5v figure 43. gain vs. frequency v ss i cm w b v dd dut gnd a nc = no connect nc ?15v gnd +15v nc +15 v +15v ?15v ?15v gnd gnd gnd 07675-037 figure 44. common-mode leakage current
ad5293 rev. d | page 18 of 24 theory of operation the ad5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the patented 1% resistor tolerance feature helps to minimize the total rdac resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the rdac register can be programmed with any position setting via the standard serial peripheral interface (spi) by loading the 16-bit data-word. serial data interface the ad5293 contains a serial interface ( sync , sclk, din, and sdo) that is compatible with spi standards, as well as most dsps. the device allows data to be written to every register via the spi. shift register the ad5293 shift register is 16 bits wide (see figure 2 ). the 16-bit data-word consists of two unused bits, which are set to 0, followed by four control bits and 10 rdac data bits. data is loaded msb first (bit 15). the four control bits determine the function of the software command (see table 11 ). figure 3 shows a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. the sync pin must be held low until the complete data-word is loaded from the din pin. when sync returns high, the serial data-word is decoded according to the instructions in . the command bits (cx) control the operation of the digital potentiometer. the data bits (dx) are the values that are loaded into the decoded register. the ad5293 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. for example, the ad5293 works with a 32-bit word, but it cannot work properly with a 31- or 33-bit word. the ad5293 does not require a continuous sclk, when table 11 sync is high, and all interface pins should be operated close to the supply rails to minimize power consumption in the digital input buffers. rdac register the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with all zeros, the wiper is connected to terminal b of the variable resistor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. the rdy pin can be used to monitor the completion of a write to or read from the rdac register. the ad5293 presets to midscale on power-up. write protection on power-up, the serial data input register write command for the rdac register is disabled. the rdac write protect bit, c1 of the control register (see tabl e 12 and table 13 ), is set to 0 by default. this disables any change of the rdac register content, regardless of the software commands, except that the rdac register can be refreshed to midscale using the software reset command (command 3, see table 11 ) or through hardware, using the reset pin. to enable programming of the variable resistor wiper position (programming the rdac register), the write protect bit, c1 of the control register, must first be programmed. this is accomplished by loading the serial data input register with command 4 (see ). table 11 basic operation the basic mode of setting the variable resistor wiper position (programming the rdac register) is accomplished by loading the serial data input register with command 1 (see table 11 ) and the desired wiper position data. the rdy pin can be used to monitor the completion of this rdac register write command. command 2 can be used to read back the contents of the rdac register (see table 11 ). after issuing the readback command, the rdy pin can be monitored to indicate when the data is available to be read out on sdo in the next spi operation. instead of monitoring the rdy pin, a minimum delay can be implemented when executing a write or read command (see table 5 ). tabl e 9 provides an example listing of a sequence of serial data input (din) words with the serial data output appearing at the sdo pin in hexadecimal format for an rdac write and read. table 9. rdac register write and read din sdo action 0x1802 0xxxxx 1 enable update of wiper position. 0x0500 0x1802 write 0x100 to the rdac register. wiper moves to ? full-scale position. 0x0800 0x0500 prepare data read from rdac register. 0x0000 0x0100 nop (instruction 0) sends a 16-bit word out of sdo, where the last 10 bits contain the contents of the rdac register. 1 x = unknown. shutdown mode the ad5293 can be placed in shutdown mode by executing the software shutdown command (see command 6 in table 11 ), and setting the lsb to 1. this feature places the rdac in a special state in which terminal a is open-circuited and wiper w is connected to terminal b. the contents of the rdac register are unchanged by entering shutdown mode. however, all commands listed in table 11 are supported while in shutdown mode.
ad5293 rev. d | page 19 of 24 reset a low-to-high transition of the hardware reset pin loads the rdac register with midscale. the ad5293 can also be reset through software by executing command 3 (see ). the control register is restored with default bits (see ). table 11 table 13 resistor performance mode this mode activates a new, patented 1% end-to-end resistor tolerance that ensures a 1% resistor tolerance on each code, that is, code = half scale, r wb =10 k 100 . see table 2 and table 4 to verify which codes achieve 1% resistor tolerance. the resistor performance mode is activated by programming bit c2 of the control register (see table 12 and table 13 ). the typical settling time is shown in figure 32 . sdo pin and daisy-chain operation the serial data output pin (sdo) serves two purposes: it can be used to read the contents of the wiper setting and control register using command 2, and command 5, respectively (see table 11 ) or the sdo pin can be used in daisy-chain mode. data is clocked out of sdo on the rising edge of sclk. the sdo pin contains an open-drain n-channel fet that requires a pull-up resistor if this pin is used. to place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by command 0 should be sent to the part. table 10 provides a sample listing for the sequence of the serial data input (din). daisy chaining mini- mizes the number of port pins required from the controlling ic. as shown in figure 45 , users need to tie the sdo pin of one package to the din pin of the next package. users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the sdo-to-din interface may require additional time delay between subsequent devices. when two ad5293s are daisy-chained, 32 bits of data are required. the first 16 bits go to u2, and the second 16 bits go to u1. the sync pin should be held low until all 32 bits are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. keep the sync pin low until all 32 bits are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. din sdo sclk sclk r p 2.2k ? din sdo u1 u2 ad5293 ad5293 sync v logic micro- controller sclk ss mosi sync 07675-039 figure 45. daisy-chain configuration using sdo table 10. minimize power dissipation at the sdo pin din sdo 1 action 0xxxxx 0xxxxx last user command sent to the digipot 0x8001 0xxxxx prepares the sdo pin to be placed in high impedance mode 0x0000 high impedance the sdo pi n is placed in high impedance 1 x = dont care. table 11. command operation truth table command bits[b13:b10] data bits[b9:b0] 1 command c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x nop command. do nothing. 1 0 0 0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to rdac. 2 0 0 1 0 x x x x x x x x x x read rdac wiper setting from sdo output in the next frame. 3 0 1 0 0 x x x x x x x x x x reset. refresh rdac with midscale code. 4 0 1 1 0 x x x x x x x d2 d1 x write contents of serial register data to control register. 5 0 1 1 1 x x x x x x x x x x read control register from sdo output in the next frame. 6 1 0 0 0 x x x x x x x x x d0 software power-down. d0 = 0 (normal mode). d0 = 1 (device placed in shutdown mode). 1 x = dont care. table 12. control register bit map d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x 1 x 1 x 1 x 1 x 1 x 1 x 1 c2 c1 x 1 1 x = dont care.
ad5293 rev. d | page 20 of 24 table 13. control register function register name bit name description control c2 calibration enable. 0 = resistor performance mode (default). 1 = normal mode. c1 rdac register write protect. 0 = locks the wiper position thro ugh the digital interface (default). 1 = allows update of wiper position through digital interface. rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5293 employs a 3-stage segmentation approach, as shown in figure 46 . the ad5293 wiper switch is designed with transmission gate cmos topology and with the gate voltage derived from v dd . r w s w w r w 10-bit address decoder a r l r l r m r m b r m r m r l r l 07675-040 figure 46. simplifi ed rdac circuit programming the variable resistor rheostat operation1% resistor tolerance the ad5293 operates in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be left floating or it can be tied to the w terminal, as shown in figure 47 . w a b w a b w a b 07675-041 figure 47. rheostat mode configuration the nomin a l resist anc e b e twe e n ter min a l a and ter min a l b, r ab , is available in 20 k, 50 k, and 100 k and has 1024 tap points that are accessed by the wiper terminal. the 10-bit data in the rdac latch is decoded to select one of the 1024 possible wiper settings. the ad5293 contains an internal 1% resistor tolerance calibration feature that can be enabled or disabled, enabled by default by programming bit c2 of the control register (see table 12 and table 13 ). the digitally programmed output resistance between the w terminal and the a terminal, r wa , and the w terminal and b terminal, r wb , is calibrated to give a maximum of 1% absolute resistance error over both the full supply and temperature ranges. as a result, the general equation for determining the digitally programmed output resistance between the w terminal and b terminal is ab wb r d dr = 1024 )( (1) where: d is the decimal equivalent of the binary code loaded in the 10-bit rdac register. r ab is the end-to-end resistance. similar to the mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa is also calibrated to give a maximum of 1% absolute resistance error. r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equation for this operation is ab wa r d dr ? = 1024 1024 )( (2) where: d is the decimal equivalent of the binary code loaded in the 10-bit rdac register. r ab is the end-to-end resistance. in the zero-scale condition, a finite total wiper resistance of 120 is present. regardless of the setting in which the part is operating, care should be taken to limit the current between the a terminal to b terminal, the w terminal to the a terminal, and the w terminal to the b terminal to the maximum continuous current of 3 ma or to the pulse current specified in table 6 . otherwise, degradation, or possible destruction of the internal switch contact, can occur.
ad5293 rev. d | page 21 of 24 programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper-to-b terminal and wiper-to-a terminal that is proportional to the input voltage at a to b, as shown in figure 48 . unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. 07675-042 w a b v in v out figure 48. potentiometer mode configuration if ignoring the effect of the wiper resistance for simplicity, connecting the a terminal to 30 v and the b terminal to ground produces an output voltage at the wiper w to terminal b that ranges from 0 v to 30 v ? 1 lsb. each lsb of voltage is equal to the voltage applied across the a terminal and b terminal, divided by the 1024 positions of the potentiometer divider. the general equation defining the output voltage at v w , with respect to ground for any valid input voltage applied to terminal a and terminal b, is b a w v d v d dv ? += 1024 1024 1024 )( (3) to optimize the wiper position update rate when in voltage divider mode, it is recommended that the internal 1% resistor tolerance calibration feature be disabled by programming bit c2 of the control register (see tabl e 11 ). operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r wa and r wb , and not on the absolute values. therefore, the temperature drift reduces to 5 ppm/c. ext_cap capacitor a 1 f capacitor to gnd must be connected to the ext_cap pin (see figure 49 ) on power-up and throughout the operation of the ad5293. this capacitor must have a voltage rating of 7 v. ad5293 gnd c1 1f ext_cap 07675-043 figure 49. hardware setup for the ext_cap pin terminal voltage operating range the positive v dd and negative v ss power supplies of the ad5293 define the boundary conditions for proper 3-terminal, digital potentiometer operation. supply signals present on the a, b, and w terminals that exceed v dd or v ss are clamped by the internal forward-biased diodes (see figure 50 ). v ss v dd a w b 07675-044 figure 50. maximum terminal voltages set by v dd and v ss the ground pin of the ad5293 is primarily used as a digital ground reference. to minimize the digital ground bounce, the ad5293 ground pin should be joined remotely to common ground. the digital input control signals to the ad5293 must be referenced to the device ground pin (gnd) to satisfy the logic level defined in the specifications section. power-up sequence because there are diodes to limit the voltage compliance at the a, b, and w terminals (see figure 50 ), it is important to power v dd and v ss first, before applying any voltage to the a, b, and w terminals. otherwise, the diode is forward-biased such that v dd and v ss are powered up unintentionally. the ideal power-up sequence is gnd, v ss , v logic , v dd , the digital inputs, and then v a , v b , and v w . the order of powering up v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd , v ss , and v logic . regardless of the power-up sequence and the ramp rates of the power supplies, the power-on preset activates after v logic is powered, restoring midscale to the rdac register.
ad5293 rev. d | page 22 of 24 applications information high voltage dac the ad5293 can be configured as a high voltage dac, with an output voltage as high as 33 v. the circuit is shown in figure 51 . the output is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 2 1v2.1 1024 )( r r d dv out (4) where d is the decimal code from 0 to 1023. ad5293 u2 ad8512 v+ v? ad8512 v out v dd u1b v dd r bias a dr512 d1 r 2 r 1 b 20k u1a 07675-153 figure 51. high voltage dac programmable voltage source with boosted output for applications that require high current adjustments, such as a laser diode or turnable laser, a boosted voltage source can be considered (see figure 52 ). w signal c c r bias ld v in a b v out u1 ad5293 u3 2n7002 u2 i l op184 07675-155 figure 52. programmable boosted voltage source in this circuit, the inverting input of the op amp forces v out to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n-channel fet (u3). the n-channel fet power handling must be adequate to dissipate (v in ? v out ) i l power. this circuit can source a maximum of 100 ma with a 33 v supply. high accuracy dac it is possible to configure the ad5293 as a high accuracy dac by optimizing the resolution of the device over a specific reduced voltage range. this is achieved by placing external resistors on either side of the rdac, as shown in figure 53 . the improved 1% resistor tolerance specification greatly reduces error associated with matching to discrete resistors. 3 1024 )1024( 1 1024 3 )( )( )( rr r vr r dv ab d dd ab d out + + + = ? (5) ad5293 u1 v out b r 2 20k r 1 r 3 1% op1177 v+ v? v dd v dd u2 07675-154 figure 53. optimizing resolution variable gain instrumentation amplifier the ad8221 in conjunction with the ad5293 and the adg1207, as shown in figure 54 , make an excellent instrumentation amplifier for use in data acquisition systems. the data acquisition system is low distortion and low noise enable it to condition signals in front of a variety of adcs. ad8221 ad5293 +v in1 v dd v out v ss a dg1207 +v in4 ?v in1 ?v in4 07675-156 figure 54. data acquisition system the gain can be calculated by using equation 6, as follows: ab rd dg += )1024( k 4.49 1)( (6)
ad5293 rev. d | page 23 of 24 audio volume control the excellent thd performance and high voltage capability of the ad5293 make it ideal for digital volume control. the ad5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. to prevent this, a zero-crossing window detector can be inserted to the cs line to delay the device update until the audio signal crosses the window. because the input signal can operate on top of any dc level, rather than absolute 0 v level, zero crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. the configuration to reduce zipper noise is shown in figure 56 , and the results of using this configuration are shown in figure 55 . the input is ac-coupled by c1 and attenuated down before feeding into the window comparator formed by u2, u3, and u4b. u6 is used to establish the signal as zero reference. the upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 v and 2.497 v (or 0.005 v window) in this example. this output is anded with the chip select signal such that the ad5293 updates whenever the signal crosses the window. to avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one. in figure 55 , the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. channel 1 freq = 20.25khz 1.03v p-p 1 2 0 7675-158 figure 55. zipper noise detector r 1 100k ? r 2 200 ? 5v v in v+ v? ad8541 5v u6 r 3 100k ? r 4 90k ? r 5 10k ? c1 1f v dd v ss sclk sdin v+ v? ad5293 20k ? +15v ?15v c3 0.1f c2 0.1f a b w gnd sdin sclk u1 v cc gnd v cc gnd adcmp371 adcmp371 +15v ?15v +5v +5v u3 u2 v out u5 u4a u4b 16 2 4 5 7408 7408 sync sync 07675-157 figure 56. audio volume control with zipper noise reduction.
ad5293 rev. d | page 24 of 24 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 57. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters ordering guide model 1 r ab (k) resolution temperature range package description package option ad5293bruz-20 20 1,024 ?40c to +105c 14-lead tssop ru-14 ad5293bruz-20-rl7 20 1,024 ?40c to +105c 14-lead tssop ru-14 ad5293bruz-50 50 1,024 ?40c to +105c 14-lead tssop ru-14 ad5293bruz-50-rl7 50 1,024 ?40c to +105c 14-lead tssop ru-14 ad5293bruz-100 100 1,024 ?40c to +105c 14-lead tssop ru-14 AD5293BRUZ-100-RL7 100 1,024 ?40c to +105c 14-lead tssop ru-14 1 z = rohs compliant part. ?2009C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07675-0-3/11(d)

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